This invention generally relates to photolithographic patterning processes and more particularly to a method for reducing photo-induced charge accumulation in a process wafer to reduce or avoid defect producing electrical discharge or arcing phenomena in semiconductor manufacturing processes.
As devices become smaller and integration density increases, reactive ion etching (RIE) has become a key process in anisotropic etching of semiconductor features. RIE or ion-enhanced etching works by a combination of physical and chemical mechanisms for achieving selectivity and anisotropicity during the etching process. Generally, plasma assisted anisotropic etching operates in the milliTorr and above range. Generally three processes compete with each other during plasma etching; physical bombardment by ions, chemical etching by radicals and ions, and surface passivation by the deposition of passivating films. In some applications, for example, etching high aspect ratio features such as vias, high density plasma (HDP) etching which has a higher density of ions and operates at lower pressures has been increasingly used in etching high aspect ratio features, for example, with aspect ratios greater than about 3:1.
Another plasma process common in semiconductor manufacturing are plasma assisted chemical vapor deposition (CVD) assisted techniques, including PECVD and HDP-CVD. In particular, high density plasma (HDP) processes, such as electron cyclotron resonance (ECR) processes and induced coupling plasma (ICP) processes have been found to produce high-quality low dielectric constant (e.g.,  less than 3.0) carbon doped silicon oxide. Generally, HDP-CVD provides a high density of low energy ions resulting in higher quality films at lower deposition temperatures, compared to for example, PECVD. HDP-CVD is particularly ideal for forming inter-metal dielectric (IMD) insulating oxide layers because of its superior gap filling capability.
An increasingly problematical phenomenon in manufacturing multi-level semiconductor devices is charge accumulation along dielectric insulating layer surfaces and near surface regions as a result of the various semiconductor manufacturing processes including plasma assisted processes such as deposition and anisotropic etching. Depending on the various process parameters such as RF power and bias power, impacting ions and radical may cause the accumulation of charge within the dielectric insulating layers due to charge imbalances caused by non-uniformities in the plasma and charge non-uniformities caused by the etching target. For example, charged species may become incorporated within the surface of the layer, with localized charge accumulation aided by defects formed in the dielectric insulating layer. In addition, ion and radical bombardment may increase the concentration of charged defects at localized portions of the surface, thereby increasing localized charge buildup within the dielectric layer. In addition, conductive interconnect pathways aid the movement of electrical charge preferentially to particular areas of the process wafer. As dielectric insulating layers have decreased in dielectric constant, a corresponding decrease in mechanical strength and hardness properties has lowered the dielectric breakdown threshold. In addition, as feature sizes decrease, the electric field increases for the same amount of charge accumulation or charge imbalance, making dielectric breakdown more likely. Further, lower dielectric constant materials are increasing able to maintain charge imbalance accumulations for longer periods of time. The electrical charge imbalance accumulation and movement to localized areas of the semiconductor wafer also includes a relatively slow on-going time dependent process following charge imbalance creating processes such as RIE.
The problem of arcing or electrical discharge has increasingly become a critical problem for both RIE processes and other semiconductor processes creating electrical charge imbalances in the semiconductor wafer including dielectric insulating layers. In many cases, the charge imbalance accumulation exists for long time periods, for example hours, periodically resulting in spontaneous dielectric breakdown or arcing even in the absence of plasma processes, also referred to as time dependent dielectric arcing (TDDA). The electrical discharge is typically accompanied by mechanical failure causing damage to dielectric including localized micro-cracking.
Arcing damage frequently occurs in the dielectric insulator/metal conductor interfaces, where conductive interconnect lines provide an electrical pathway to preferentially move electrical charges to resulting a localized charge imbalance region in the dielectric insulating layer. The problem is critical since the damage caused by arcing is frequently severe enough to make further processing of the wafer impractical or seriously impact reliability. As a result, arcing damage to the wafer is costly in terms of wafer yield and reliability.
There is therefore a need in the semiconductor processing art to develop a method whereby charge imbalance accumulation in semiconductors is reduced such that arcing including during time dependent dielectric arcing (TDDA) is reduced or avoided thereby avoiding arcing induced defects to the semiconductor wafer to improve wafer yield and device reliability.
It is therefore an object of the invention to provide a method whereby charge imbalance accumulation in semiconductors is reduced such that arcing including during time dependent dielectric arcing (TDDA) is reduced or avoided thereby avoiding arcing induced defects to the semiconductor wafer to improve wafer yield and device reliability while overcoming other shortcomings and deficiencies of the prior art.
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a method for reducing electrical charge imbalances in a semiconductor process wafer.
In a first embodiment, the method includes providing a semiconductor process wafer including a dielectric insulating layer; exposing the semiconductor process wafer to a semiconductor process whereby an electrical charge imbalance accumulates in charge imbalance portions of the dielectric insulating layer; and, treating the semiconductor process wafer with a controlled atmosphere of treatment gas including at least one of inert gas and hydrogen to reduce an accumulated charge imbalance in the charge imbalance portions.
These and other embodiments, aspects and features of the invention will be better understood from a detailed description of the preferred embodiments of the invention which are further described below in conjunction with the accompanying Figures.